SystemC在CPU/GPU验证中的应用（六）

       摘要：下面分享50个逐步升级SystemC编程能力的示例及建议的学习路线图。您可以一次一批地完成它们——从前五个基础的例子开始，然后转向channels, TLM, bus models, simple CPU/GPU kernels等等。在每个阶段掌握之后，再进行下一组的学习。

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50个代表性的SystemC例子

1. Hello, SystemC! (module + sc_main)
2. Simple clock generator
3. 4-bit up/down counter
4. Blocking FIFO channel
5. Non-blocking handshake channel
6. Combinational AND/OR modules
7. D-flip‐flop with async reset
8. 8×1 multiplexer
9. Simple RAM model (blocking accesses)
10. Simple ROM model
11. Dual-port RAM
12. Bus arbiter (round-robin)
13. TLM2.0 blocking transport (initiator)
14. TLM2.0 blocking transport (target)
15. TLM2.0 non-blocking transport
16. TLM2.0 analysis port / export
17. Simple AXI-Lite bus model
18. AXI-Lite master + slave example
19. Quantum keeper & time annotation
20. tlm_utils::simple_initiator_socket
21. tlm_utils::simple_target_socket
22. Hierarchical module instantiation
23. Dynamic process spawn & kill
24. Event notification & sc_event_queue
25. Reset synchronization circuit
26. Clock domain crossing FIFO
27. Bus monitor / tracer (TLM analysis)
28. Memory-mapped register file
29. Interrupt controller model
30. Pipeline stage model (fetch/decode/execute)
31. Simple 4-stage CPU datapath
32. Cache model (direct-mapped)
33. DMA engine model
34. GPGPU kernel launcher skeleton
35. GPU shader core (vector add)
36. Barrier synchronization (sc_barrier emulation)
37. Producer-consumer with sc_mutex
38. sc_semaphore example
39. SystemC-AMS basic RC filter
40. Fixed-point arithmetic with sc_fixed
41. Power‐aware sc_trace (VCD generation)
42. Cross-trade-off analysis (timing vs. power)
43. SystemC assertions (SC_ASSERT)
44. UVM-SystemC basic use case
45. Co-simulation stub (Verilog DPI)
46. SystemC Python binding stub
47. Parameterized module (SC_MODULE_T)
48. TLM-2.0 generic payload extensions
49. Simple NoC router model
50. Full mini‐SOC: CPU + L2 cache + memory + interconnect

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Sixth Batch: Examples 41–50

Below are the first five examples with complete code + detailed comments.

41. Power‐aware sc_trace (VCD 生成)

文件名：trace_example.cpp

#include <systemc.h>

// 简单的 4-bit 计数器模块，每个时钟周期递增
SC_MODULE(Counter) {
    sc_in<bool>        clk;
    sc_out<sc_uint<4>> count;

    SC_CTOR(Counter) {
        SC_METHOD(proc);
        sensitive << clk.pos();
        count.initialize(0);
    }

    void proc() {
        count.write( count.read() + 1 );
    }
};

int sc_main(int, char*[]) {
    sc_clock       clk("clk", 10, SC_NS);
    sc_signal<sc_uint<4>> cnt_sig;

    Counter cnt("cnt");
    cnt.clk(clk);
    cnt.count(cnt_sig);

    // 打开 VCD 波形文件
    sc_trace_file* tf = sc_create_vcd_trace_file("wave");
    // 跟踪时钟和计数值
    sc_trace(tf, clk,    "clk");
    sc_trace(tf, cnt_sig,"count");

    // run 200ns
    sc_start(200, SC_NS);

    sc_close_vcd_trace_file(tf);
    return 0;
}

运行后会生成 wave.vcd，可以在 GTKWave 等工具中查看。

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42. Cross‐trade‐off Analysis (Timing vs. Power 简易模型)

文件名：power_analysis.cpp

#include <systemc.h>

// 统计翻转次数并估算功耗的模块
SC_MODULE(Gate) {
    sc_in<bool> in;
    sc_out<bool> out;
    unsigned long toggle_count;

    SC_CTOR(Gate): toggle_count(0) {
        SC_METHOD(proc);
        sensitive << in;
        dont_initialize();
    }

    void proc() {
        bool new_v = !in.read(); // 反相
        if (out.read() != new_v) {
            toggle_count++;
            out.write(new_v);
        }
    }
};

// 顶层 Testbench：记录仿真时间、开关次数并估算能耗
int sc_main(int, char*[]) {
    sc_clock    clk("clk", 10, SC_NS);
    sc_signal<bool> sig_in, sig_out;

    Gate gate("gate");
    gate.in(sig_in);
    gate.out(sig_out);

    // 产生输入信号——一个 4 周期高电平，4 周期低电平循环
    SC_THREAD([&]() {
        while (true) {
            for (int i = 0; i < 4; ++i) { sig_in.write(true);  wait(clk.posedge_event()); }
            for (int i = 0; i < 4; ++i) { sig_in.write(false); wait(clk.posedge_event()); }
        }
    });

    // 在仿真结束时打印结果
    sc_start(200, SC_NS);
    unsigned long toggles = gate.toggle_count;
    double sim_time_ns = sc_time_stamp().to_seconds() * 1e9;
    d